Honored Contributor
Honored ContributorI think that you find what I was missing:
--- Quote Start --- Variables are not accessible by the simulator. Although the compiler is generating registered signals for variables in some cases, signals should be used for data that is intended to keep it's value between clock cycles. --- Quote End --- It could explains why in some cases my code is working and sometimes it does not. I was thinking I knew when I had to use a signal and when I had to use a variable, but it is apparently still a problem for me ^^. Concerning the complexity of my code I think that is because I use to coding in languages such as c or java which is a bad habit if you want to progress in vhdl :-S. I will modify this and let you know about that thank you very much :-)
