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Thanks for answering so quickly!
Actually, I am working on a project which has not been created by me. By "constrain your design" do you mean that I have to set some parameters before any compilation, or just specify a clock, and an input waveform for the .vwf files?
Maybe this could help us to answer this question: I am able to create regularly an image of the gate array and to download it on my fpga to test my code, and some functionality works well (so I assume that the design is "constrained").
Thank you again for your help
Denis
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Hi Dennis,
lets start from the basics. What kind of design description do you use Verilog ,VHDL,
schematic ... ? Did you get warnings from Quartus ? Which device are you using .....
Kind regards
GPK
Honored Contributor
