Toplevel Simulation Control Signal And Retain Post-Fit Netlist

I am working on a large CycloneIII design using QuartusII v9.0.

In our design we have a toplevel input simulation control signal that is routed to various aspects of the design. This simulation control signal overrides specific elements of the design that would require a lot of simulation time e.g. timers, reset periods etc. Therefore when we build the design for the target application we want to force the simulation control signal in to a disabled state while for simulating the design we wish to have control of this signal and retain the post fit simulation netlist.

In the past we have routed the simulation control signal to a specific pin on the target board and disabled the functionality at the pin i.e. grounded on the PCB. For our latest design I wish to retain the toplevel simulation control input signal but avoid using a physical pin that is not used in the target application.

If I assign the simulation control signal as a virtual pin it retains the post fit netlist (i.e. it does not optimise out the simulation control aspects) but I can't find how I can force a logic level on it. Does it default to a certain state?

Or is there a better way of doing this i.e. generics etc?

Thanks.