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Altera_Forum
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15 years ago

Toplevel Simulation Control Signal And Retain Post-Fit Netlist

I am working on a large CycloneIII design using QuartusII v9.0. In our design we have a toplevel input simulation control signal that is routed to various aspects of the design. This simulation...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

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I think this would still cause a problem in the target hardware if a virtual pin results in a floating input as you cannot guarantee the input level, thus this would be sampled and ripple through reg1->reg2-> to the simulation control signal.

Can someone confirm that a virtual pin results in a disconnected signal i.e. left floating in the target FPGA?

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It will not propagate due to the latching. Once pin is zero (of floating states) it will be latched by reg2 and reg2 will no longer see the pin