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Altera_Forum
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15 years ago

Toplevel Simulation Control Signal And Retain Post-Fit Netlist

I am working on a large CycloneIII design using QuartusII v9.0. In our design we have a toplevel input simulation control signal that is routed to various aspects of the design. This simulation...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

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It will not propagate due to the latching. Once pin is zero (of floating states) it will be latched by reg2 and reg2 will no longer see the pin

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Yeah sorry as you said it does indeed guard against a logic '1' propagating so this would be useful.

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If you look in the Technology Map Viewer in Post-Fitting mode you can find the LUT you mention, but it has a '0' feeding out ...

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That is perfect to prove the point on what QuartusII is assigning that node because it wouldn't be nice leaving parts of the design with virtual pins floating.

Thanks.