Timing-Driven Synthesis is skipped because it could not initialize the timing netlist

Using DCFIFO IP with standard settings causes timing-driven synthesis to be skipped and seems to create some timing issues in the design (optimizing of cells that should not me optimized). Warning message:

Warning (330000): Timing-Driven Synthesis is skipped because it could not initialize the timing netlist

I have found the cause of the warning, instantiating a FIFO (v22.1) with the default option checked. "Generate SDC files and disable embedded constraint". Disabling that option seems to restore the execution of timing-driven synthesis. I would think this is a bug, since this option is checked by default and even recommended by Intel to reach timing for high-freq DCFIFO (https://www.intel.com/content/www/us/en/docs/programmable/683522/18-0/dcfifo-timing-constraint-setting.html).

I'm worried that unchecking this option also introduces incorrect false paths as mentioned here: https://www.intel.com/content/www/us/en/support/programmable/articles/000084486.html

Am I right to worry? Is there anything else I should know?

Quartus Prime version: Version 22.1std.2 Build 922 07/20/2023 SC Standard Edition

FPGA: Arria 10

IP settings: attached (option that causes issue unchecked)