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OlaG's avatar
OlaG
Icon for New Contributor rankNew Contributor
3 years ago

Timing-Driven Synthesis is skipped because it could not initialize the timing netlist

Using DCFIFO IP with standard settings causes timing-driven synthesis to be skipped and seems to create some timing issues in the design (optimizing of cells that should not me optimized). Warning me...
Hdl
Timing
ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
3 years ago

Hi,


It's recommended to check the option "Generate SDC files and disable embedded constraint". If not, keeping it unchecked will cause FIFO hardware failure for high frequency design.

Based on internal feedback, it's safe to ignore the warning as it wouldn't affect much on FIFO functional and timing.


Thanks,

Best Regards,

Sheng