Forum Discussion

OlaG's avatar
OlaG
Icon for New Contributor rankNew Contributor
2 years ago

Timing-Driven Synthesis is skipped because it could not initialize the timing netlist

Using DCFIFO IP with standard settings causes timing-driven synthesis to be skipped and seems to create some timing issues in the design (optimizing of cells that should not me optimized). Warning me...
Hdl
Timing
ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
2 years ago

Hi,


Based on internal team, you may ignore the warning as it is not going to cause any functional issue and not affecting much.


Let me know if it causes IP timing not met or any performance degradation issue.


Thanks,

Sheng


OlaG's avatar
OlaG
Icon for New Contributor rankNew Contributor
2 years ago

Dear Sheng,

Thank you for your quick feedback! I am a little surprised since this message seems to indicate that optimization could merge registers with incompatible timing, according to

"Timing-Driven Synthesis prevents registers with incompatible timing constraints from merging for any Optimization Technique setting." in https://www.intel.com/content/www/us/en/docs/programmable/683283/18-1/enabling-timing-driven-synthesis.html

What does the internal team recommend, to keep the option "Generate SDC files and disable embedded constraint" checked or not? Are there any detrimental effects of keeping it unchecked?