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OlaG's avatar
OlaG
Icon for New Contributor rankNew Contributor
3 years ago

Timing-Driven Synthesis is skipped because it could not initialize the timing netlist

Using DCFIFO IP with standard settings causes timing-driven synthesis to be skipped and seems to create some timing issues in the design (optimizing of cells that should not me optimized). Warning me...
Hdl
Timing
ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
3 years ago

Hi,


I had reported this issue to internal team. I'll come back to you once there's any further feedback from internal team. Please allow some time for investigating.


Thanks,

Best Regards,

Sheng