Timing Analyzer Inter-Path-Competition in Nios sub-system

I am trying to close out timing in my Arria-10 FPGA design, using Quartus Prime V19.1.0 pro edition.
I clicked on the link to "report timing closure recommendations" This opened Timing Analyzer which reports "Inter-path-Competition" with 18 paths affected

This is the first recommendation:

★★★★★
Duplicate the nodes specified in the details for the path from u0|nilm_nios|nios...ss_line_field[4]u0|nilm_nios|nios2_gen2_2|cpu|d_address_line_field[4] to u0|nilm_onchip_me...m_block1a30~reg0u0|nilm_onchip_memory|onchip_memory2_1|the_altsyncram|auto_generated|ram_block1a30~reg0
Issue: Inter-path Competition
From: u0|nilm_nios|nios2_gen2_2|cpu|d_address_line_field[4]
To: u0|nilm_onchip_memory|onchip_memory2_1|the_altsyncram|auto_generated|ram_block1a30~reg0
Timing Analysis: report timing
Nodes to duplicate:
u0|nilm_nios|nios2_gen2_2|cpu|d_address_line_field[4]
u0|mm_interconnect_0|router|reduce_nor_11
u0|nilm_onchip_memory|onchip_memory2_1|the_altsyncram|auto_generated|decode3|rtl~0
★★★★★

So the path that is affected is between my Nios processor (nilm_nios) and its associated onchip memory (nilm_onchip_memory)
Since both of these modules are created and connected within Platform Designer, I can not see how to duplicate the specified nodes.
Can anyone suggest how I might resolve this error?

Thanks!
Chris