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CWarr1
New Contributor
New ContributorTiming Analyzer Inter-Path-Competition in Nios sub-system
I am trying to close out timing in my Arria-10 FPGA design, using Quartus Prime V19.1.0 pro edition. I clicked on the link to "report timing closure recommendations" This opened Timing Analyzer whic...
KhaiChein_Y_Intel
Regular Contributor
Regular ContributorHi,
You may also duplicate the register using Manual Logic Duplication in Assignment editor. You may find example in FPGA Wiki page https://community.intel.com/t5/FPGA-Wiki/Register-Duplication-for-Timing-Closure/ta-p/735917 and document https://www.intel.com/content/dam/altera-www/global/en_US/uploads/a/aa/Register_Duplication_for_Timing_Closure.pdf
Thanks
Best regards,
KhaiY
