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CWarr1's avatar
CWarr1
Icon for New Contributor rankNew Contributor
5 years ago

Timing Analyzer Inter-Path-Competition in Nios sub-system

I am trying to close out timing in my Arria-10 FPGA design, using Quartus Prime V19.1.0 pro edition. I clicked on the link to "report timing closure recommendations" This opened Timing Analyzer whic...
KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,


We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you


Best regards,

KhaiY