Yogesh
Occasional Contributor
Occasional ContributorTiming achieved by a single DSP is more than frequency given in document?
I have instantiated a sigle multiplier as below:
`timescale 1 ns / 1 ps
module modules(clk,
rst,
i_conv_clken,
i_input_data_a,
i_input_data_b,
o_mult_result );
input clk,rst,i_conv_clken;
input signed [7:0] i_input_data_a,i_input_data_b;
output reg signed[20:0] o_mult_result;
wire [15:0] out;
lp_mult lp_mult_component (
.clock(clk),
.clken(i_conv_clken),
.dataa (i_input_data_a),
.datab (i_input_data_b),
.result (out)
);
always@(posedge clk or negedge rst)
begin
if(!rst)
begin
o_mult_result<=0;
end
else
begin
o_mult_result<= out;
end
end
endmoduleconstraints - 500 Mhz
read_sdc -hdl
create_clock -name clk -period 2 [get_ports {clk}]
Results I got is:
Fmax=906Mhz
Restricted Fmax=605Mhz
but in below document its mentioned that an independent 9x9 multiplier can achieve 300 Mhz max in cyclone V GT.
page 44 in below document:
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-v/cv_51002.pdf
So, am I doing something wrong in knowing the max frequency that can be achieved in cyclone V GT?
If yes how to find out the max frequency of a DSP in cyclone v GT?
