Forum Discussion
Hi,
If you locate the node in the Chip Planner, you will see that the register is outside of the DSP. Thus, this is not limited by the performance of the DSP.
Changing the DSP pipeline to 3, you will see that the result_extra0_reg[15:0] that is located in the DSP requires 3.225 for the min period
Thanks.
Best regards,
KhaiY
- Yogesh5 years ago
Occasional Contributor
Hi,
I have modified my code and is facing new issue with resect to DSP resource utilization.
I am sharing archieve of my sample code.
Here I have instantiated 48 lpm_mult IP. Each lpm_mult takes two 8 bit inputs , and will provide 16 bit output.
Ideally tool should use 16 DSPs since each DSP in cyclone V has three 9x9 multipliers.
But it is using 24 DSPs(with each DSP using sum of two 18x18 multipliers)
If this is the case ,I will face shortage of DSPs in my top level.
So, I want the tool to use three 9x9 for each DSP(since i am only doing 8x8 multiplication).
1)I thought tool might be using more since its available, but it is not the case.Say If i instantiate 685 9x9 multipliers , It will use 342 DSPs(100 % usage- each DSP using sum of two 18x18), and for one more 9x9(i.e 685 th multiplier) it will use ALMs.
As a result there is drop in my required frequency . Tool should have used 3 9x9 atleast in this case since there are no more DSPs, to achieve required design right?
2) Am I doing something wrong in the instantiation , so that tool is not understanding that it should use 1 DSP for 3 instances of 9x9 lpm_mults? If yes, please tell me how to make tool use it so?
3) I want to know how to use DSPs in different operational modes mentionaed in below document (page number 3-10)
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-v/cv_5v2.pdf
Please help me with this issue.
Thankyou,
regards.
Yogesh