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Yogesh's avatar
Yogesh
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

Timing achieved by a single DSP is more than frequency given in document?

I have instantiated a sigle multiplier as below: `timescale 1 ns / 1 ps module modules(clk, rst, i_conv_clken, i_input_data_a, i_input_data_b, o_mult_re...
KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi,

If you locate the node in the Chip Planner, you will see that the register is outside of the DSP. Thus, this is not limited by the performance of the DSP.

Changing the DSP pipeline to 3, you will see that the result_extra0_reg[15:0] that is located in the DSP requires 3.225 for the min period

Thanks.

Best regards,

KhaiY