Timing achieved by a single DSP is more than frequency given in document?

Hi Yogesh,

If you locate the path that failed timing in the Chip Planner, you will notice that the path is in the core logic area but not inside the IP. As explained earlier, this is not limited by the DSP performance, you have to look into each of the path and see why it fails to meet the desired frequency.

Take an example of From node: conv_unit:conv_inst10|bias[10], To node: conv_unit:conv_inst10|accumulator_1[14]~DUPLICATE, you can see that both node are not located inside the DSP (Grey color block)

I notice that you constrained the clock only without constraining the I/O port. Even if you get the STA clean result after fixing the violation, the design might not operate as intended as you didnt consrain how the FPGA interact with external device. In this case, you have to make sure that the all the necessary constraints are added in the SDC, then you can start to fix the timing violation in the failing path.

You may refer to Intel Quartus Prime Timing Analyzer Cookbook : https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl_timequest_cookbook.pdf. This document explains how to constrain clock, I/O port, and some timing exceptions that you might want to apply in the design.

Thanks.

Best regards,

KhaiY