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Yogesh's avatar
Yogesh
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

Timing achieved by a single DSP is more than frequency given in document?

I have instantiated a sigle multiplier as below: `timescale 1 ns / 1 ps module modules(clk, rst, i_conv_clken, i_input_data_a, i_input_data_b, o_mult_re...
KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi Yogesh,

The initial question is about the timing Fmax of the design with DSP; it has been answered. Can you create a new forum post for new question? This is to make sure that each forum post has only one question so that other customers with the similar question/issue/problem can find the solution/explanation easily.

Thanks.

Best regards,

KhaiY