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Yogesh's avatar
Yogesh
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Timing achieved by a single DSP is more than frequency given in document?

I have instantiated a sigle multiplier as below: `timescale 1 ns / 1 ps module modules(clk, rst, i_conv_clken, i_input_data_a, i_input_data_b, o_mult_re...
KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,

The verilog above instantiate lp_mult; the source file for the lp_mult is required in order to compile the design. Could you provide the design QAR for investigation? To create the QAR file, click on Project > Archive Preoject > Archive.

Thanks.

Best regards,

KhaiY

  • Yogesh's avatar
    Yogesh
    Icon for Occasional Contributor rankOccasional Contributor
    5 years ago

    Hi,

    Please find the qar file as requested.

    Thankyou