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Honored Contributor
Honored ContributorThis verilog code does not work on FPGA
Hi, I'm new here, so if there's anything wrong with my post, please, feel free to tell me.
I'm taking logic design class at my school, learning to design logic gates and verilog, and trying it on FPGA. My recent assignment was about building a coffee machine that takes in 100, 500, 1000 cash up to 2000. (The money we're using here is Korean money, so don't get confused with dollars.) It has coffee-out and change-out button. One cup of coffee costs 600. I'm using SW[0]~SW[4] for the money-in and the other buttons, and SW[9] as a reset button. The following code compiled without any errors on Quartus and the wave forms came out correctly on ModelSim. But it did not work on FPGA. The board that we're using in our class is Cyclone III EP3C16F484C6 -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
module lab7(
input reg SW,
input reg CLOCK_50,
output reg HEX0_D, HEX1_D, HEX3_D);
reg cs, ns, pulse, a;
reg sum;
wire mod10;
wire h, f, t, cff, chg;
//set wires for each input
assign h = SW; //hundred won
assign f = SW; //five hundred won
assign t = SW; //thousand won
assign cff = SW; //coffee out
assign chg = SW; //change out
//state parameters
parameter s0 = 0;
parameter s1 = 1;
//mealy FSM one pulse generator
always@(*)
a = SW ? 0 : h || f || t || cff;
always@(posedge CLOCK_50, posedge SW)
begin
if (SW) cs <= s0;
else cs <= ns;
end
always@(*)
begin
case(cs)
s0:begin
ns = a ? s1 : s0;
pulse = a;
end
s1:begin
ns = a ? s1 : s0;
pulse = 0;
end
endcase
end
//end of FSM
//sum of money
always@(*)
begin
if(SW||chg) sum = 0; //initialization and when change out button is on
else if (sum<0)
sum = 0; //negative numbers are set to zero
else if (sum<21)
begin
if(h) //add hundred won
sum = pulse ? sum + 1 : sum;
else if(f) //add five hundred
sum = pulse ? sum + 5 : sum;
else if(t) //add thousand
sum = pulse ? sum + 10 : sum;
else if(cff&&sum>5) //coffee out and subtract by 6 only if sum>5
sum = pulse ? sum - 6 : sum;
else sum = sum;
end
else sum = 20; //sum greater than 20 are set to 20
end
//output for HEX0_D
assign mod10 = sum%10; //sum on one's position
always@(*)
begin
case(mod10)
0 : HEX0_D = 7'b100_0000; //0
1 : HEX0_D = 7'b111_1001; //1
2 : HEX0_D = 7'b010_0100; //2
3 : HEX0_D = 7'b011_0000; //3
4 : HEX0_D = 7'b001_1001; //4
5 : HEX0_D = 7'b001_0010; //5
6 : HEX0_D = 7'b000_0010; //6
7 : HEX0_D = 7'b111_1000; //7
8 : HEX0_D = 7'b000_0000; //8
9 : HEX0_D = 7'b001_1000; //9
endcase
end
//output for HEX1_D
always@(*)
begin
if(sum<10) HEX1_D = 7'b100_0000; //0
else if(sum<20) HEX1_D = 7'b111_1001; //1
else HEX1_D = 7'b010_0100; //2
end
//output for HEX3_D
always@(*)
begin
if (sum<6) HEX3_D = 7'b100_0000; //0
else if (sum<12) HEX3_D = 7'b111_1001; //1
else if (sum<18) HEX3_D = 7'b010_0100; //2
else HEX3_D = 7'b011_0000; //3
end
endmodule
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
According to the professor, I'm using an asyncronous design on the 'sum of money' part, which we haven't covered on our lessons yet.
I realized that I assigned the values so that sum feeds back itself without any flip-flops.
So I changed that part just a little:
//sum of money
always@(posedge CLOCK_50, posedge SW, posedge chg)
begin
if(SW||chg) sum <= 0; //initialization and when change out button is on
else if (sum<0)
sum <= 0; //negative numbers are set to zero
else if (sum<20)
begin
if(h) //add hundred won
sum <= pulse ? sum + 1 : sum;
else if(f) //add five hundred
sum <= pulse ? sum + 5 : sum;
else if(t) //add thousand
sum <= pulse ? sum + 10 : sum;
else if(cff&&sum>5) //coffee out and subtract by 6 only if sum>5
sum <= pulse ? sum - 6 : sum;
else sum <= sum;
end
else sum <= 20; //sum greater than 20 are set to 20
end
