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Altera_Forum's avatar
Altera_Forum
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10 years ago

This verilog code does not work on FPGA

Hi, I'm new here, so if there's anything wrong with my post, please, feel free to tell me. I'm taking logic design class at my school, learning to design logic gates and verilog, and tryi...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Have you tried Design Assistant Tool which is a part of Quartus II software? I believe it gives you some advices.

http://quartushelp.altera.com/15.0/mergedprojects/verify/da/comp_view_doctor.htm

Here are some hints for you.

1) Other than CLOCK_50 and sw[9], all signals must be synchronous to CLOCK_50 otherwise you will see malfunction in the real world. Don't do "if(h)".

2) Signal Tap II, which is also a part of Quartus II software, is a very powerful tool which allows us to monitor signals on the hardware. You can see what happens in the FPGA.

3) I'm not sure if you have leant anti-chatter circuit. If input signals are connected to external push buttons or switches, you must remove chatter.