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Have you tried Design Assistant Tool which is a part of Quartus II software? I believe it gives you some advices.
http://quartushelp.altera.com/15.0/mergedprojects/verify/da/comp_view_doctor.htm Here are some hints for you.
1) Other than CLOCK_50 and sw[9], all signals must be synchronous to CLOCK_50 otherwise you will see malfunction in the real world. Don't do "if(h)".
2) Signal Tap II, which is also a part of Quartus II software, is a very powerful tool which allows us to monitor signals on the hardware. You can see what happens in the FPGA.
3) I'm not sure if you have leant anti-chatter circuit. If input signals are connected to external push buttons or switches, you must remove chatter.
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I never knew there was an Assistant Tool lol. I'll try that right away and update the post as soon as I get the results
1) I haven't gone through asynchronous design in my class yet, so I don't understand how making the asynchronous causes problems on the circuit board.
But I got some good feedbacks from other replies; maybe I'll try those first and see what's gonna happen.
2) The FPGA that I'm using in the class is actually the professor's lab equipment. I'll try that feature on my next try.
3) I haven't learned about anti-chatter circuit.
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