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Altera_Forum
Honored Contributor
Honored ContributorThis verilog code does not work on FPGA
Hi, I'm new here, so if there's anything wrong with my post, please, feel free to tell me. I'm taking logic design class at my school, learning to design logic gates and verilog, and tryi...
Altera_ForumHonored Contributor
Honored ContributorSry I forgot to post that
The thread is updated with the problem explanation at the bottom (For some reason, I can't view the edited post above; hope it comes up later)
