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Altera_Forum
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10 years ago

This verilog code does not work on FPGA

Hi, I'm new here, so if there's anything wrong with my post, please, feel free to tell me. I'm taking logic design class at my school, learning to design logic gates and verilog, and tryi...
Altera_Forum's avatar
Altera_Forum
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10 years ago

The Sum value is unregistered, meaning you'll have a logic loop in your design. Ie. one input to the adder is it's own output, meaning it will do the sum over and over again depending on the delay through the adder.

You need to register the sum value.