This verilog code does not work on FPGA

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The Sum value is unregistered, meaning you'll have a logic loop in your design. Ie. one input to the adder is it's own output, meaning it will do the sum over and over again depending on the delay through the adder.

You need to register the sum value.

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That's actually what my professor told me, except he explained it with tons of details that I had no idea about.

I'll try to change the "sum of money" part a little more so it doesn't get the loop.

Thank you for the reply