The wait function

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doesn't work

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is no clear problem specification.

Presuming you are talking about Verilog for hardware synthesis rather than simulation, you are probably trying a non-synthesizable Verilog construct. Timing statements and level sensitive events are generally ignored for synthesis.

always

wait (event)

begin

...

end

That's ok!

Be careful with

always wait(for_expression_to_be_true) begin ... end

You will get a simulation hang once for_expression_to_be_true becomes true, unless the code inside the begin/end does something to make for_expression_to_be_true become false.

Then you really want to use @(clk) or @(posdedge clk), instead of wait(clk). @(expression) means 'wait for a change in expression'.

Otherwise, you would have to write

always wait(!clk) wait(clk) begin ... end