Altera_Forum
Honored Contributor
Honored ContributorThe wait function
Hello, I was wondering, can I use the wait function in Verilog? It seems like it simply doesn't work My syntax is wait (event) begin ... end Thanks a lot
Forum Discussion
Altera_ForumHonored Contributor
Honored ContributorBe careful with
always wait(for_expression_to_be_true) begin ... end You will get a simulation hang once for_expression_to_be_true becomes true, unless the code inside the begin/end does something to make for_expression_to_be_true become false.
