Altera_Forum
Honored Contributor
Honored ContributorThe wait function
Hello, I was wondering, can I use the wait function in Verilog? It seems like it simply doesn't work My syntax is wait (event) begin ... end Thanks a lot
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Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- doesn't work --- Quote End --- is no clear problem specification. Presuming you are talking about Verilog for hardware synthesis rather than simulation, you are probably trying a non-synthesizable Verilog construct. Timing statements and level sensitive events are generally ignored for synthesis.
