Altera_Forum
Honored Contributor
Honored ContributorThe wait function
Hello, I was wondering, can I use the wait function in Verilog? It seems like it simply doesn't work My syntax is wait (event) begin ... end Thanks a lot
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Altera_ForumHonored Contributor
Honored ContributorThen you really want to use @(clk) or @(posdedge clk), instead of wait(clk). @(expression) means 'wait for a change in expression'.
Otherwise, you would have to write always wait(!clk) wait(clk) begin ... end
