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Altera_Forum's avatar
Altera_Forum
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13 years ago

The wait function

Hello, I was wondering, can I use the wait function in Verilog? It seems like it simply doesn't work My syntax is wait (event) begin ... end Thanks a lot
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

for_expression_to_be_true also can be an input, such as, clk .etc;