The report timing of TimeQuet Timing Analyzer

Is there anyone have the specification about the report timing which will explain what's the meaning of the paramter such as IC,Cell,Count.

thank you in advance!

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In the process of learn TimeQuet Timing Analyzer I fall in trouble.

According to the "data required time = latch edge + clock network delay to destination register – μtsu" the μtSU should on the left of the latch edge(like the picture 1),but the μtSU is on the right of the latch edge in the report timing of TimeQuest Timing Analyzer(like the picture 2).It's inconceivable!

Thank you!

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Picture 1 seems to show the Data Arrival while TimeQuest puts it on the Data required. It does not really matter if you add uTsu to the Data Arrival, or subtract it from the Data Required. At the end, slack = Data Required - Data Arrival, so as long as uTsu is accounted somewhere, you are fine.

My recommendation is not to try to worry about these details. The uTsu is constant so you can basically ignore it when trying to understand timing. At the end, all you care is if the Data Arrival is smaller than the Data Required, in which case, you have positive slack, and a working system. Otherwise, you need to find a way to shorten the data path until you meet that equation.

Hope this helps.

DK

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Is there anyone have the specification about the report timing which will explain what's the meaning of the paramter such as IC,Cell,Count.

thank you in advance!

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This is a summary page giving you statistics about your timing path. Cell represents the portion of the delay going through logic blocks, while IC represents the portion of the delay going through routing. This is important in FPGAs as it can indicate if you just have a place and route problem (too much IC delay) in which case you could solve it by helping the fitter keep the logic close by, or if you have too much cell delay, in which case you likely need to go to your source files and change the design (e.g. add pipelining).

The count simply tells you how many blocks (or routing hops) you have. In your example, you have three logic elements connected by two routing connections.

Hope this helps.

DK

Hi!davka:

in the process of learning timing analysis,I notice that the count of IC and Cell will change alone with the variation of clock frequency.could you give some suggestions about that?

thank you in advance!

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Hi!davka:

in the process of learning timing analysis,I notice that the count of IC and Cell will change alone with the variation of clock frequency.could you give some suggestions about that?

thank you in advance!

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I will need to see more details (Family, compiler options), but Quartus has both Timing Driven Synthesis (newer families) and Physical Synthesis which will change the synthesized design based on timing constraints. You can also clearly see how the fitter keep delays smaller when needed. This is all called "Timing Driven Compilation", where Quartus (Synthesis, Place and Route engines) will make smart decisions based on the timing slack of each path.

DK

I have found that in the Quartus II Integrated Synthesis PDF.

thank you very much!

Hi Davlka

In the process of learning SDR Source-Synchronous Output,I found that the output delay max and the output delay min are hard to be understand.you can see that the output delay min occurs before the latch edge and the output delay max occurs after the latch edge.So I think the output delay max shoud be Th

and the output delay min should be -Tsu.

Could you give some suggestion?

thank you very much!