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Altera_Forum
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15 years ago

The report timing of TimeQuet Timing Analyzer

In the process of learn TimeQuet Timing Analyzer I fall in trouble. According to the "data required time = latch edge + clock network delay to destination register – μtsu" the μtSU shoul...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Hi Davlka

In the process of learning SDR Source-Synchronous Output,I found that the output delay max and the output delay min are hard to be understand.you can see that the output delay min occurs before the latch edge and the output delay max occurs after the latch edge.So I think the output delay max shoud be Th

and the output delay min should be -Tsu.

Could you give some suggestion?

thank you very much!