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Is there anyone have the specification about the report timing which will explain what's the meaning of the paramter such as IC,Cell,Count.
thank you in advance!
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This is a summary page giving you statistics about your timing path. Cell represents the portion of the delay going through logic blocks, while IC represents the portion of the delay going through routing. This is important in FPGAs as it can indicate if you just have a place and route problem (too much IC delay) in which case you could solve it by helping the fitter keep the logic close by, or if you have too much cell delay, in which case you likely need to go to your source files and change the design (e.g. add pipelining).
The count simply tells you how many blocks (or routing hops) you have. In your example, you have three logic elements connected by two routing connections.
Hope this helps.
DK
Honored Contributor
