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Hi!davka:
in the process of learning timing analysis,I notice that the count of IC and Cell will change alone with the variation of clock frequency.could you give some suggestions about that?
thank you in advance!
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I will need to see more details (Family, compiler options), but Quartus has both Timing Driven Synthesis (newer families) and Physical Synthesis which will change the synthesized design based on timing constraints. You can also clearly see how the fitter keep delays smaller when needed. This is all called "Timing Driven Compilation", where Quartus (Synthesis, Place and Route engines) will make smart decisions based on the timing slack of each path.
DK
Honored Contributor
