The report timing of TimeQuet Timing Analyzer

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In the process of learn TimeQuet Timing Analyzer I fall in trouble.

According to the "data required time = latch edge + clock network delay to destination register – μtsu" the μtSU should on the left of the latch edge(like the picture 1),but the μtSU is on the right of the latch edge in the report timing of TimeQuest Timing Analyzer(like the picture 2).It's inconceivable!

Thank you!

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Picture 1 seems to show the Data Arrival while TimeQuest puts it on the Data required. It does not really matter if you add uTsu to the Data Arrival, or subtract it from the Data Required. At the end, slack = Data Required - Data Arrival, so as long as uTsu is accounted somewhere, you are fine.

My recommendation is not to try to worry about these details. The uTsu is constant so you can basically ignore it when trying to understand timing. At the end, all you care is if the Data Arrival is smaller than the Data Required, in which case, you have positive slack, and a working system. Otherwise, you need to find a way to shorten the data path until you meet that equation.

Hope this helps.

DK