Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

The report timing of TimeQuet Timing Analyzer

In the process of learn TimeQuet Timing Analyzer I fall in trouble. According to the "data required time = latch edge + clock network delay to destination register – μtsu" the μtSU shoul...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Hi!davka:

in the process of learning timing analysis,I notice that the count of IC and Cell will change alone with the variation of clock frequency.could you give some suggestions about that?

thank you in advance!