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Altera_Forum's avatar
Altera_Forum
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11 years ago

The combinational process in VHDL

We can discuss the combinational logic in VHDL using process as following:

comb : process(vindex)

begin

if (vindex < 59 or vindex > 120) then

s_mtvalid <='1';

else

s_mtvalid <= s_fifo_mtvalid;

end if;

end process comb;

In this case, there is only "vindex" in sensitive list. If "vindex" doesn't change, it keeps a constant (e.g. 62), whether "s_mtvalid" will keep changing with "s_fifo_mtvalid" toggling?

In simulation, my answer is no, since "s_fifo_mtvalid" is not inside the senstive list. If "vindex' keeps constant, the process will not be triggered. Is this correct?

But what happen if this process is synthesised? Will this be synthesised to a correct selective comb logic?

Thanks in advance.

6 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    for modelsim simulation all signals that are read inside a process must be nicely written in its sensitivity list.

    For synthesis it doesn't seem to matter and you can examine the rtl viewer or run signaltap or quartus simulator.
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    This kind of code shows why you have to be very carfull with combinatorial processes.

    Even better, keep all processes synchronous, and any async logic outside of processes.

    s_mtvalid <= '1' when (vindex < 59 or vindex > 120) else s_fifo_mtvalid;

    Doing this implies a process with all signals on the RHS in the sensitivity list.
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Thanks very much, both of you.

    Yes, Tricky, I prefer the syntax without process. It is similar as the conditional assign in Verilog.
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    If you want to do it in a process, you can, if you use vhdl 2008, use process(all). I find this a lot less typing and saves time on debugging. But you must be aware of combinatorial loops since this could "hang" the simulator.

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Run Quartus Analysis & Synthesis, Quartus will issue a warning if a signal is missing in the sensitivity list.

    Or Use a good VHDL editor: e.g. the Sigasi VHDL editor will warn you, while you type your code. But even then run Analysis & Synthesis before simulating, it will find some other consistencies (which Modelsim eventually finds too)