Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

The combinational process in VHDL

We can discuss the combinational logic in VHDL using process as following: comb : process(vindex) begin if (vindex < 59 or vindex > 120) then s_mtvalid <='1'; else s_mtvali...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

for modelsim simulation all signals that are read inside a process must be nicely written in its sensitivity list.

For synthesis it doesn't seem to matter and you can examine the rtl viewer or run signaltap or quartus simulator.