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Altera_Forum
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11 years ago

The combinational process in VHDL

We can discuss the combinational logic in VHDL using process as following: comb : process(vindex) begin if (vindex < 59 or vindex > 120) then s_mtvalid <='1'; else s_mtvali...
Altera_Forum's avatar
Altera_Forum
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11 years ago

Run Quartus Analysis & Synthesis, Quartus will issue a warning if a signal is missing in the sensitivity list.

Or Use a good VHDL editor: e.g. the Sigasi VHDL editor will warn you, while you type your code. But even then run Analysis & Synthesis before simulating, it will find some other consistencies (which Modelsim eventually finds too)