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Altera_Forum
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11 years ago

The combinational process in VHDL

We can discuss the combinational logic in VHDL using process as following: comb : process(vindex) begin if (vindex < 59 or vindex > 120) then s_mtvalid <='1'; else s_mtvali...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

This kind of code shows why you have to be very carfull with combinatorial processes.

Even better, keep all processes synchronous, and any async logic outside of processes.

s_mtvalid <= '1' when (vindex < 59 or vindex > 120) else s_fifo_mtvalid;

Doing this implies a process with all signals on the RHS in the sensitivity list.