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Altera_Forum
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11 years ago

The combinational process in VHDL

We can discuss the combinational logic in VHDL using process as following: comb : process(vindex) begin if (vindex < 59 or vindex > 120) then s_mtvalid <='1'; else s_mtvali...
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Altera_Forum
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11 years ago

Thanks very much, both of you.

Yes, Tricky, I prefer the syntax without process. It is similar as the conditional assign in Verilog.