Occasional Contributor
Super ContributorHi Barry,
starting with your last question, yes a design recompilation is required when you change the list of acquired signals or signal options (trigger- , data-, storage enable, storage qualifier). Also when changing sample depth, type of trigger logic or any power-up trigger parameter. Changing the trigger doesn't require recompilation if all involved signals have already trigger enable set. Chosing acquired signals and signal options thoughfully avoids frequent recompilation.
I use regularly only pre-synthesis signals for Signal Tap. Finding signals respectively making it visible for Signal Tap can be tricky though. You referred to "keep" synthesis attribute, but it's only applicable for combinational nodes. Registers need "preserve" or "noprune" in case of fanout-free registers (e.g. pure debug registers). Output signals of a sub module can be tapped at the source.
Regards
Frank
Occasional ContributorHI Frank,
Thanks very much for your answers ! Right OK so only use pre-synthesis signals in Signal Tap. I get that and will do that from now on. Ok so again thanks for the tip about using preserve on registers and only using keep on combinatorial signals, i didn't know about that. For example then for a register called timer_tic_running we can have the following options to preserve that register:
NOT (* keep = "true" *) logic timer_tic_running;
YES (* preserve = "true" *) logic timer_tic_running;
YES(* noprune = "true" *) logic timer_tic_running;
Is this also OK:
MAYBE (* preserve = "true, noprune = "true" *) logic timer_tic_running;
However when you say 'changing the trigger conditions' doesn't require a rapid recompile, sometimes in my case it does do. For example if i have trig1 = 1 and trig2 = 0 and change that to trig1 = 1 and trig2 = 1 Siganl Tap GUI asks me to do a quick recomplie, which always ends up doing a full FPGA compileation. This is the behaviour i think is odd. But your saying this should not occur ? Strange because for me it does !
Thanks for your Help,
Dr Barry H
Super ContributorWhere are you changing the trigger conditions?
In the Node List, for a trigger condition column, if it's a Boolean AND trigger, you can right-click any of the cells in that column (individual signal or [bus] group) and change the value without having to recompile. You just have to start the logic analyzer running again to look for the new trigger condition.
So what exactly are you changing that it is forcing you to recompile? Screenshot would help.
Occasional ContributorHIU sstrell,
Thanks for the reply and analysis. Actually i am changing the trigger conditions from AND to OR and that causes this 'rapid recompilation' condition in Signal Tap, the . The instance manager row goes to RED in other words. This i find strange because why should that change require an FPGA compilation ? Surely the logic to do a Basic AND / Basic OR / Conditional Compare trigger operation is already compiled into Signal Tap Logic ? This does not happen using the AMD/Xilinx Chip Scope / Vivaodo scope for example.
Cheers, Dr Barry H
Super ContributorThat’s your issue. You can’t switch the trigger type between Boolean AND and OR without recompiling. The user guide lists the “runtime” changes you can make without having to recompile.
