TCL/python script to check single/multiple verilog file(s) for improper or incorrect connections

Is it feasible to write a TCL/py script which will check single/multiple verilog file(s) for improper or incorrect connections:

1. A signal var (usually input) attached to a module instance inside a container module to a (valid) port (of instance) which has not been declared either as wire or reg in the container module.
2. A signal var (usually output) which is connected to a module instance, but it is not driven by or connected to (by any of the instance module's output) either as a reg or wire.
3. Incorrectly interchanging wires to instances.
4. There may be more cases of connectivity errors introduced due to programmer's mistake, but right now these are the ones that come to my mind.

I have seen some times that the synthesis engine detects such issues and starts optimizing the design for any regs or nets which are not connected, it will start reducing/eliminating them.

These kind of mistakes are very frequent, where people writing HDL codes sometimes miss making the proper connections and/or make incorrect connections, which results in the design not working the way it should have worked.

Is there any utility in the Quartus Prime SW which can check for such mistakes or is it possible to write a user defined script which can be run every time before compiling the design?