ContributionsMost RecentMost LikesSolutionsRe: Automated connectivity check in Quartus Prime Pro No, Thank you for asking. Re: Automated connectivity check in Quartus Prime ProThank you for answering! I should be coming back in 2 working days to accept this as solution. I understand that custom script support is too much an ask, but what the demo script provides me is the objects that can then be used in my custom script.Automated connectivity check in Quartus Prime Pro In a considerably big project, there could be multiple HDL module hierarchies, where, in each hierarchy, multiple individual modules have been instantiated. Suppose Hierarchy A has following modules: B1, B2, B3. A -> (B1, B2, B3). Hierarchy C has: D1, D2, D3. C -> (D1, D2, D3). Suppose an output signal (wire/net) Q from B1 goes to D2 via B1 -> A -> B -> D2, then I can check this connectivity in either post-synthesis RTL Viewer or post-fit technology map viewer. I want to write a script such that I specify the source output port at B1 and destination input port at D2 and the script should return TRUE if both ports are found connected post synthesis. How do I do this in Quartus Prime Pro? SolvedRe: Placement constraints for PLL in QPPHi, I'm able to place the node in the assignment editor, select location option and provide the desired HSSIPMA location which was found through the Chip Planner. My question now is that the PLL is actually part of a hard IP. Which is spread across various blocks. How do I take that hard IP to move it to some other location?Re: Placement constraints for PLL in QPP Hi, I really regret my delayed response. I'll be replying back to you within next 48 hours on if your latest suggestion helps me. Re: Placement constraints for PLL in QPP There's no "Placement" option in the assignment name drop-down. QPP 20.1 Re: Placement constraints for PLL in QPPIf I refer QPP settings file reference manual, what type of settings should be used to ensure desired PLL placement?Re: Placement constraints for PLL in QPPI could see following cmd in qsf file: set_instance_assignment -name RESERVE_REGION "coordinates" -to PLL_instance. set_instance_assignment -name RESERVE_PLACE_REGION OFF -to PLL_instance For the second cmd, I changed it to ON and reran the Fit - Plan, but still same message is displayed.Re: Placement constraints for PLL in QPPWill try this and let you know.Placement constraints for PLL in QPPThere is the feature called as logic lock which can fix placement of a node, I want to know if it is possible to use logic lock for fixing position of PLL? I get a warning in plan stage of fitter as "ATX/FPLL is not placed in the same bank as reference clock." Device family: Arria 10Solved