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Re: Automated connectivity check in Quartus Prime Pro
Thank you for answering! I should be coming back in 2 working days to accept this as solution. I understand that custom script support is too much an ask, but what the demo script provides me is the objects that can then be used in my custom script.1.1KViews0likes0CommentsAutomated connectivity check in Quartus Prime Pro
In a considerably big project, there could be multiple HDL module hierarchies, where, in each hierarchy, multiple individual modules have been instantiated. Suppose Hierarchy A has following modules: B1, B2, B3. A -> (B1, B2, B3). Hierarchy C has: D1, D2, D3. C -> (D1, D2, D3). Suppose an output signal (wire/net) Q from B1 goes to D2 via B1 -> A -> B -> D2, then I can check this connectivity in either post-synthesis RTL Viewer or post-fit technology map viewer. I want to write a script such that I specify the source output port at B1 and destination input port at D2 and the script should return TRUE if both ports are found connected post synthesis. How do I do this in Quartus Prime Pro?Solved1.3KViews0likes6CommentsRe: Placement constraints for PLL in QPP
Hi, I'm able to place the node in the assignment editor, select location option and provide the desired HSSIPMA location which was found through the Chip Planner. My question now is that the PLL is actually part of a hard IP. Which is spread across various blocks. How do I take that hard IP to move it to some other location?1.4KViews0likes0CommentsRe: Placement constraints for PLL in QPP
I could see following cmd in qsf file: set_instance_assignment -name RESERVE_REGION "coordinates" -to PLL_instance. set_instance_assignment -name RESERVE_PLACE_REGION OFF -to PLL_instance For the second cmd, I changed it to ON and reran the Fit - Plan, but still same message is displayed.1.8KViews0likes0CommentsPlacement constraints for PLL in QPP
There is the feature called as logic lock which can fix placement of a node, I want to know if it is possible to use logic lock for fixing position of PLL? I get a warning in plan stage of fitter as "ATX/FPLL is not placed in the same bank as reference clock." Device family: Arria 10Solved2KViews0likes11Comments