Automated connectivity check in Quartus Prime Pro

In a considerably big project, there could be multiple HDL module hierarchies, where, in each hierarchy, multiple individual modules have been instantiated.

Suppose

Hierarchy A has following modules: B1, B2, B3.

A -> (B1, B2, B3).

Hierarchy C has: D1, D2, D3.

C -> (D1, D2, D3).

Suppose an output signal (wire/net) Q from B1 goes to D2 via B1 -> A -> B -> D2, then I can check this connectivity in either post-synthesis RTL Viewer or post-fit technology map viewer.

I want to write a script such that I specify the source output port at B1 and destination input port at D2 and the script should return TRUE if both ports are found connected post synthesis.

How do I do this in Quartus Prime Pro?