Occasional ContributorYou can choose "Location" for that version of Quartus Prime.
Regular ContributorFrom my opinion, logic lock will reduce the flexibility for you on the timing side of the design. My suggestion is you need to change the PLL location through the qsf assignments.
Occasional ContributorOccasional ContributorOccasional ContributorRegular ContributorHi,
I don't think that is the correct cmd in the qsf that relates with the PLL placement.
You can check Assignment Editor. From there, you can choose the PLL pin --> choose Placement in the Assignment Name --> choose the PLL that locate in the same bank with the reference clock.
Occasional ContributorThere's no "Placement" option in the assignment name drop-down. QPP 20.1
Regular ContributorYou can choose "Location" for that version of Quartus Prime.
Regular ContributorHello,
I wish to follow up with you regarding the issue. Do you able to moving forward with the recommendation?
Or do you need more support on this?
Regards,
Aqid
Regular ContributorAs we do not receive any response from you on the previous reply provided. Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.
Occasional ContributorHi, I really regret my delayed response. I'll be replying back to you within next 48 hours on if your latest suggestion helps me.
Occasional Contributor
