Solved
Forum Discussion
AqidAyman_Altera
Regular Contributor
1 year agoFrom my opinion, logic lock will reduce the flexibility for you on the timing side of the design. My suggestion is you need to change the PLL location through the qsf assignments.
- Pack_of_lone_wolves1 year ago
Occasional Contributor
Will try this and let you know. - Pack_of_lone_wolves1 year ago
Occasional Contributor
I could see following cmd in qsf file:
set_instance_assignment -name RESERVE_REGION "coordinates" -to PLL_instance.
set_instance_assignment -name RESERVE_PLACE_REGION OFF -to PLL_instance
For the second cmd, I changed it to ON and reran the Fit - Plan, but still same message is displayed. - Pack_of_lone_wolves1 year ago
Occasional Contributor
If I refer QPP settings file reference manual, what type of settings should be used to ensure desired PLL placement?