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Pack_of_lone_wolves's avatar
Pack_of_lone_wolves
Icon for Occasional Contributor rankOccasional Contributor
2 years ago
Solved

Placement constraints for PLL in QPP

There is the feature called as logic lock which can fix placement of a node, I want to know if it is possible to use logic lock for fixing position of PLL? I get a warning in plan stage of fitter as "...
Hdl
  • AqidAyman_Altera's avatar
    AqidAyman_Altera
    2 years ago

    You can choose "Location" for that version of Quartus Prime.


AqidAyman_Altera's avatar
AqidAyman_Altera
Icon for Regular Contributor rankRegular Contributor
2 years ago

As we do not receive any response from you on the previous reply provided. Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


  • Pack_of_lone_wolves's avatar
    Pack_of_lone_wolves
    Icon for Occasional Contributor rankOccasional Contributor
    2 years ago

    Hi, I really regret my delayed response. I'll be replying back to you within next 48 hours on if your latest suggestion helps me.

  • Pack_of_lone_wolves's avatar
    Pack_of_lone_wolves
    Icon for Occasional Contributor rankOccasional Contributor
    2 years ago
    Hi, I'm able to place the node in the assignment editor, select location option and provide the desired HSSIPMA location which was found through the Chip Planner.

    My question now is that the PLL is actually part of a hard IP. Which is spread across various blocks. How do I take that hard IP to move it to some other location?