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AqidAyman_Altera
Regular Contributor
1 year agoFrom my opinion, logic lock will reduce the flexibility for you on the timing side of the design. My suggestion is you need to change the PLL location through the qsf assignments.
Pack_of_lone_wolves
Occasional Contributor
1 year agoIf I refer QPP settings file reference manual, what type of settings should be used to ensure desired PLL placement?