TCL/python script to check single/multiple verilog file(s) for improper or incorrect connections

Hi,

Probably can check those mistakes through synthesis tool error and warnings.

Like 1. A signal var (usually input) attached to a module instance inside a container module to a (valid) port (of instance) which has not been declared either as wire or reg in the container module.

The tool probably will throw out error like object "" on left-hand side of assignment must have a variable data type

Like 2. A signal var (usually output) which is connected to a module instance, but it is not driven by or connected to (by any of the instance module's output) either as a reg or wire.

The tool will throw out warning in synthesis report (.syn.rpt) under section Top Causes of Logic Optimized Away During Sweep like Output port "" in instance "" of entity "" does not have a driver. Connecting to the default value "gnd"

As for 3. Incorrectly interchanging wires to instances., easier way is to check through rtl simulation by writing some testing senario in testbench.

Thanks,

Best regards,

Sheng