Forum Discussion
Occasional ContributorTCL/python script to check single/multiple verilog file(s) for improper or incorrect connections
Hi,
Probably can check those mistakes through synthesis tool error and warnings.
Like 1. A signal var (usually input) attached to a module instance inside a container module to a (valid) port (of instance) which has not been declared either as wire or reg in the container module.
The tool probably will throw out error like object "" on left-hand side of assignment must have a variable data type
Like 2. A signal var (usually output) which is connected to a module instance, but it is not driven by or connected to (by any of the instance module's output) either as a reg or wire.
The tool will throw out warning in synthesis report (.syn.rpt) under section Top Causes of Logic Optimized Away During Sweep like Output port "" in instance "" of entity "" does not have a driver. Connecting to the default value "gnd"
As for 3. Incorrectly interchanging wires to instances., easier way is to check through rtl simulation by writing some testing senario in testbench.
Thanks,
Best regards,
Sheng
Occasional ContributorThank You for answering my question, it helps, turns out that I found out about this phenomenon exactly through the synthesis report, but wondered if there is any other way to automatically make sure that things like that don't happen or get detected and notified? Only when I had a look at them, I sensed something unusual but I'm not sure if I saw any specific warning out of the sea of warning messages.
Super Contributor
@Pack_of_lone_wolves wrote:Thank You for answering my question, it helps, turns out that I found out about this phenomenon exactly through the synthesis report, but wondered if there is any other way to automatically make sure that things like that don't happen or get detected and notified? Only when I had a look at them, I sensed something unusual but I'm not sure if I saw any specific warning out of the sea of warning messages.
You can run full synthesis (Analysis & Synthesis) but this takes longer than Analysis & Elaboration. And you can filter the messages output by the compiler to focus on just errors or warnings/critical warnings with the checkboxes at the top of the Messages window.
