"Tcl error: ERROR: Argument <node_object> is an object filter that matches no objects. Specify one matches only one object." when using LVDS SERDES IP.

Hi,

I received the feedback. You may add the below constraint in the sdc file:

derive_pll_clocks -create_base_clocks

or

In the attached design, you can use the SDC generated for the example design, which already contains this SDC function call:

set_global_assignment -name SDC_FILE lvds_0_example_design/lvds_0_example_design_example_design/ed_synth.sdc

Thanks.

Best regards,

KhaiY

Hi KhaiY,

I saw the example design, however I'm already using the option "-create_base_clocks" in the directive "derive_pll_clocks".

I want to remark that the SAME design IS WORKING flawlessly in Quartus Pro 19.1, instead it fails in:

• Quartus pro 19.3
• Quartus pro 19.4
• Quartus pro 20.1

Any idea? I can provide my design if helps, or open a separate topic in the forum.

Regards.

Gabriele

Hi Gabriele,

Can you create a separate topic and provide the design in the new topic?

In Michael's design, I have tested that the error is fixed by adding the sdc constraint derive_pll_clocks -create_base_clocks

For your design, there might be other root cause and require further investigation.

Thanks.

Best regards,

KhaiY

Sure, let me try first to replicate the error with a minimal version of the design, because the project itself is quite large.

Hi,

Sure. Thanks.

Best regards,

KhaiY

Here is the new topic with attached the reduced archived version of the project.

https://forums.intel.com/s/question/0D50P00004eWYpTSAW/tcl-error-in-timing-analysis-phase-using-lvds-serdes-rx-ip

Regards.

Gabriele

Hi,

Sure. Please allow me some time to look into this in the new forum post.

Thanks

Best regards,

KhaiY

H KhaiY,

sorry for the late reply, we have some license issues on our server at the moment.

However, I have tested your solution locally and it works for the example design.

I did not expect that the sdc file is not part of the project by default. So, I did not checked this.

Adding the example sdc solved the error.

I will apply the same solution to our design now. As the synthesis will require some time, I will give you an update once it is finished.

Thank you.

Michael

Hi Michael,

May I know if you have any updates?

Thanks.

Best regards,

KhaiY

Hi KhaiY,

unfortunately, the error in our design was not solved by this solution. We still get an error in line 400 in the tcl script. However, we have changed our costom hardware during the last months resulting in an update of our design. This also affects the reference clock of the IOPLL for the lvds core. At the moment, I will update the design and check if the error still occurs. Once I get first results, I will give you an update.

Thanks.

Michael